During fabrication of an integrated-circuit devices, proper etching of the electrically conductive top layer is required outside the electrodes in order to avoid electrical short cuts during operation of the integrated-circuit device. The electrically conductive top layer may for instance form a seed metallization layer, which forms a common electrode during galvanic growth of the electrodes that connect the active areas of an integrated-circuit device to external devices.
A precise control of the etching is required to avoid an over-etching of the top layer, which would form a reliability risk.
U.S. Pat. Nos. 6,417,089 and 5,293,006 describe methods to reduce an undercutting of an under-bump metallurgy (UBM) by liquid or solid inter-diffusion between the bump material and the UBM. However, it remains difficult to detect such phenomena and to assess whether fabricated integrated-circuit devices have a high reliability risk that leads to short circuits and cracks during later operation by the end costumer.